This application claims the priority of Korean Patent Application No. 2003-55034, filed on Aug. 8, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a memory device employing a bit-line sense amplifier with an arbitrary sensing directionality by a gate bias control, and a method of amplifying voltage levels of a bit line and a complementary bit line of a memory device.
2. Description of the Related Art
In general, since dynamic random access memory (DRAM) cells do not have self amplification ability, memory cell data are sensed using bit-line sense amplifiers connected to the memory cells during read-out operation. The bit-line sense amplifiers sense and amplify a voltage difference of about 100 mV through 250 mV generated due to charge distribution in the bit lines.
A method of pre-charging bit lines and complementary bit lines to a power source voltage VDD level, and then sensing and amplifying cell data in connection with bit-line sense amplifiers of DRAMs has been disclosed. In this case, since the charge distribution does not occur in the bit lines when the cell data is “1”, the voltage difference is not generated between the bit lines and the complementary bit lines, so that it is not possible to sense the cell data. As a solution for this problem, a reference cell pre-charged to a VDD/2 level is provided to drop the voltage level of the complementary bit lines and generate the voltage difference between the bit lines and the complementary bit lines, so that it is possible to sense the cell data.
Another method of pre-charging the bit lines and the complementary bit lines to a ground voltage VSS level, and then sensing and amplifying the cell data in a bit-line sense amplifier has been disclosed. In this case, since the charge distribution does not occur in the bit lines pre-charged to the ground voltage VSS when the cell data is “0”, it is not possible to sense the cell data, so that a reference cell pre-charged to a VDD/2 level is required for sensing the cell data.
FIG. 1 is a circuit diagram illustrating a conventional bit-line sense amplifier. Referring to FIG. 1, a first memory cell 110 and a first reference cell 130 are connected to a bit line BL, and a second memory cell 120 and a second reference cell 140 are connected to a complementary bit line BLB. A bit-line equalization circuit 150 is connected between the bit line BL and the complementary bit line BLB. When a word line WL1 of the first memory cell 110 is enabled, data of the first memory cell 110 is transferred to the bit line BL, and the data of the first memory cell 110 is sensed and amplified by means of a bit-line sense amplifier 160 which senses a voltage difference between the bit line BL and the complementary bit line BLB. At this time, a word line RWL1 of the second reference cell 140 connected to the complementary bit line BLB is enabled, and a voltage level corresponding to a half of the power source voltage VDD, that is, a voltage level of VDD/2, is supplied to the complementary bit line BLB. Accordingly, the bit-line sense amplifier 160 senses a voltage level of the bit line BL by using the voltage level of VDD/2 of the complementary bit line BLB as a reference.
However, addition of the reference cells may cause the size of a memory chip to increase. In addition, when the reference cells have defects, a design technology for repairing the defective reference cells may be complex. Therefore, bit-line sense amplifiers capable of working without reference cells have been required.